D. Chaudhary, V. Muppalla, and A. Mukherjee,"Design of Low Power Stacked Inverter Based SRAM Cell with Improved Write Ability", in IEEE Region 10 Symposium (TENSYMP), pp.925-928, IEEE 2020, 10.1109/TENSYMP50017.2020.9230809       Inproceedings

A. Mukherjee and A. S. Dhar,"Triple transistor based triple modular redundancy with embedded voter circuit", Microelectronics Journal, vol.87, pp.101-109, Elsevier, May 2019, 10.1016/j.mejo.2019.03.014       Article

A. Mukherjee and A. S. Dhar,"Reliable VLSI architecture design using modulo-quad-transistor redundancy method", Circuits, Systems, and Signal Processing, vol.37, no.12, pp.5595-5615, Springer 2018, 10.1007/s00034-018-0837-1       Article

S. Banerjee, E. Sarkar, and A. Mukherjee,"Effect of fin width and fin height on threshold voltage for tripple gate rectangular finFET", Techno International Journal of Health, Engineering, Management and Science (TIJHEMS), vol.2, no.5, pp.217-220, TECHNO INDIA UNIVERSITY, WEST BENGAL 2018       Article

P. Das, A. Sinha, and A. Mukherjee,"Fault tolerant architecture design of a 4-bit magnitude comparator", in International Conference on Computer, Electrical & Communication Engineering (ICCECE), IEEE, Kolkata, India, November 2018, 10.1109/ICCECE.2017.8526235       Inproceedings

A. Mukherjee and A. S. Dhar,"Triple transistor based fault tolerance for resource constrained applications", Microelectronics Journal, vol.68, pp.1-6, Elsevier, October 2017, 10.1016/j.mejo.2017.08.005       Article

A. Mukherjee and A. S. Dhar,"Choice of granularity for reliable circuit design using dynamic reconfiguration", Microelectronics Reliability, vol.63, pp.291-303, Elsevier, August 2016, 10.1016/j.microrel.2016.04.001       Article

A. Mukherjee and A. S. Dhar,"Real-time fault-tolerance with hot-standby topology for conditional sum adder", Microelectronics Reliability, vol.55, no.3-4, pp.704-712, Elsevier, March 2015, 10.1016/j.microrel.2014.12.011       Article

A. Mukherjee and A. S. Dhar,"Fault tolerant architecture design using quad-gate-transistor redundancy", IET Circuits, Devices & Systems, vol.9, no.3, pp.152-160, IET, May 2015, 10.1049/iet-cds.2014.0106       Article

A. Mukherjee and A. S. Dhar,"Design of a fault-tolerant conditional sum adder", in Progress in VLSI Design and Test16th, vol.7373, pp.217-222, Springer, lecture notes in computer science, Shibpur, India 2012, 10.1007/978-3-642-31494-0_25       Inproceedings