Analog-to-Digital Converters (ADCs) are fundamental components in SoC and ASIC design for sensor based application, converting analog signals into digital signals for processing and analysis of input data.SAR ADC provides low power as it can utilize hardware-software codesign. Successive approximation logic requires mostly digital circuits and hence power requirements are less stringent. Among various architectures, the Successive Approximation Register (SAR) ADC stands out for its high resolution with medium to low sampling frequencies, simplicity, energy and area efficiency, and compatibility with advanced CMOS processes. SAR ADC operates based on a binary search algorithm, using a Digital-to-Analog Converter (DAC) and a comparator to iteratively determine the digital equivalent of an input signal with help of the SAR Register. The architecture of a SAR ADC typically comprises a bootstrapped switch, a capacitive DAC, a high-speed comparator, and SAR logic. During conversion, C-DAC samples the input signal and reference voltages that are required to compare. The comparator outputs a decision at each step, allowing the SAR logic to refine the digital code iteratively. This process, repeated over a number of steps equal to the ADC&rsquos resolution, makes the SAR ADC both efficient, less complicated and accurate. Despite its advantages, achieving high resolution and speed in SAR ADCs introduces several challenges. The comparator, consider as heart of the design, must provide fast and accurate decisions while minimizing noise, offset, and power consumption. Comparator is the most power consuming block of SAR ADC. Comparasion time of comparator plays vital role in deciding the speed of SAR ADC. On the other hand, the DAC switching scheme also plays an important role in power consumption, it also faces issues such as non-linearity, settling errors, and capacitor mismatches, which effect ADCs performance parameters such as INL,DNL etc. This research discusses the core structure of SAR ADCs, emphasizing the functionality of its major components and the associated design challenges. It also reviews recent advancements of comparator, DAC switching schemes, auto calibration of capacitor DAC and Digital SAR logic circuit offering insights into strategies for optimizing SAR ADCs dynamic and static performance, reducing power consumption, improving speed and shrinking the active area of the chip.