The advent of Very Large Scale Integration (VLSI) technology has revolutionized the field of electronic design, enabling the creation of complex digital circuits with millions of components on a single chip. However, the increasing complexity of VLSI circuits has created new challenges in design, verification, and optimization. CAD tools have evolved significantly over the years, incorporating advanced algorithms and techniques to tackle the complexities of VLSI design. Despite these advancements, traditional CAD tools are facing significant challenges in keeping pace with the rapid evolution of VLSI technology. This is where machine learning (ML) comes into play. ML algorithms have demonstrated remarkable capabilities in pattern recognition, predictive modeling, and optimization, making them an attractive solution for addressing the challenges of VLSI circuit design. By harnessing the power of ML algorithms, IC designers can unlock new levels of optimization, automation, and innovation, leading to transformative gains in performance, efficiency, and productivity. One key driver is the need to overcome the limitations of traditional design methodologies, which often rely on manual iteration and rule-based approaches. ML enables designers to tap into vast amounts of data, identify subtle patterns, and make predictions, allowing for more informed design decisions and reduced reliance on trial and error. In almost all CMOS circuits, the CMOS inverter is the fundamental circuit. The CMOS inverter is used as a trial circuit for application of machine learning for design. Support vector machine (SVM) and Artificial Neural Network (ANN) are used for delay and power performance modeling of CMOS inverter. Generative adversial network (GAN) is used to augment data for machine learning based modelling. The work can further be taken ahead by carrying out layout based simulation and extensive use of GAN in circuits like ring oscillator. Use of multiobjective optimization and graph neural network are also planned to be investigated.