National Institute of Technology Rourkela

राष्ट्रीय प्रौद्योगिकी संस्थान राउरकेला

ଜାତୀୟ ପ୍ରଯୁକ୍ତି ପ୍ରତିଷ୍ଠାନ ରାଉରକେଲା

An Institute of National Importance

Seminar Details

Seminar Title:
Hardware Design for Predicting Early Signs of Sudden Cardiac Arrests from ECG Signals
Seminar Type:
Defence Seminar
Department:
Electronics and Communication Engineering
Speaker Name:
Anusaka Gon ( Rollno : 518ec1002)
Speaker Type:
Student
Venue:
Offline: EC seminar hall (EC 303) Online: https://meet.google.com/ntz-kxsm-sjn (Google Meet Link)
Date and Time:
13 Feb 2025 10:30 AM
Contact:
Dr. Atin Mukherjee
Abstract:

Electrocardiogram (ECG) is a non-invasive way to record the electrical activities of the heart and is recognized by its features, P-QRS-T. Among the most fatal cardiac arrhythmias, sudden cardiac arrests (SCA) can cause death unexpectedly if left untreated, and hence, their early prediction is important. SCAs can be predicted by the detection ventricular tachycardias (VT), which are characterized by the presence of three or more consecutively occurring premature ventricular contraction (PVC) beats in an ECG signal. PVCs are classified as multifocal or unifocal, and ventricular bigeminies, ventricular trigeminies, non-sustained ventricular tachycardias (NSVT), and sustained ventricular tachycardias (SVT). In this work, a hardware-efficient FPGA-based design for predicting the early signs of SCAs is proposed by detecting PVC beats and classifying them into six major categories of ventricular arrhythmias (VAs). For pre-processing, modified lifting-based discrete wavelet transform (MLDWT) is used to combat all the ECG noises and enhance the QRS complexes in the ECG signal. For feature extraction stage, important PVC features namely R peaks, T peaks, and the Teager energy operator (TEO) are detected. With the extracted features, a characteristic matching algorithm is used for PVC detection, and an adaptive decision logic-based (ADL) classifier is utilized for VA classification, resulting in a detection accuracy rate of 98.2% when tested using the online ECG databases, viz., the MIT-BIH arrhythmia database (MITDB) and the MIT-BIH supraventricular database (SVDB). The complete SCA prediction system is implemented on the Nexys 4 DDR Artix-7 FPGA board utilizing 10.4% of the total available hardware resources. For future integration of the SCA prediction system into wearable healthcare devices, an ASIC implementation is performed, resulting in a place and route area of 0.02 mm2 and a power utilization of 3.47 µW at an operating frequency of 100 KHz when implemented using SCL 180 nm CMOS technology.