In today’s state-of-the-art VLSI circuits, the SRAMs covers a greater part of the chip area. As technology scales down and moves into the nanometer regime, memory storage elements like SRAM cells are mostly affected by the impact of radiation. Therefore, the rate of soft error generation is enhanced with technology scaling. In this work, a reliable soft error tolerant 12 transistor RTSC-12T SRAM cell is proposed that provides good radiation tolerant capability and is completely immune to SEU and SEMNU. The proposed RTSC-12T has been compared with the existing RHD12T, QUCCE12T and EDP12T by considering the design metrics such as read delay, write delay, Static Noise Margin, critical charge, static and dynamic power consumption, total area and SEU occurrence probability. The simulation has been performed in UMC 65nm CMOS technology at a temperature of 27°C. The Proposed RTSC-12T single cell SRAM exhibits 1.25x/ 1.19x shorter TRA than RHD12T/ EDP12T and 1.37x/ 1.03x lower write ability (TWA) than RHD12T/ QUCCE12T @VDD = 1V. Also, the proposed cell consumes 1.28x lower static power than QUCCE12T and 1.2x/ 1.32x lower dynamic power than QUCCE12T/ EDP12T respectively. However, these gains come at the expense of a slightly lower WSNM.