S. Pyne,"Rescheduling of power gating instructions for reduction of in-rush current", in 2018 31st International Conference on VLSI Design and 2018 17th International Conference on Embedded Systems (VLSID), pp.25-30, IEEE, Pune, India, March 2018, 10.1109/VLSID.2018.32       Inproceedings

S. Pyne,"An architectural support for reduction of in-rush current in systems with instruction controlled power gating", in GLSVLSI '18 Proceedings of the 2018 on Great Lakes Symposium on VLSI, pp.487-490, Association for Computing Machinery (ACM), Chicago, IL, USA, May 2018, 10.1145/3194554.3194645       Inproceedings

J. Swain and S. Pyne,"Deadlock detection in digital microfluidics biochip droplet routing", in Proceedings of 22nd International Symposium on VLSI Design and Test (VDAT 2018), Springer 2018       Inproceedings

S. Pyne,"Scheduling of hybrid battery-supercapacitor control instructions for longevity in systems with power gating", in ISLPED '18 Proceedings of the International Symposium on Low Power Electronics and Design, pp.6, ACM Digital Library, Seattle, WA, USA, July 2018, 10.1145/3218603.3218609       Inproceedings

S. Pyne and A. Pal,"Runtime leakage power reduction using loop unrolling and fine grained power gating", Journal of Low Power Electronics (JOLPE), vol.11, no.1, pp.16 - 36, American Scientific Publishers, March 2015, https://doi.org/10.1166/jolpe.2015.1361       Article

S. Pyne and A. Pal,"Energy efficient array computations using loop unrolling with partial gray code sequence", Journal of Low Power Electronics (JOLPE), vol.11, no.2, pp.149 - 172, American Scientific Publishers, June 2015, 10.1166/jolpe.2015.1376       Article

S. Pyne and A. Pal,"Loop unrolling with fine grained power gating for runtime leakage power reduction", in 18th International Symposium on VLSI Design and Test, pp.1-6, IEEE, PSG College of Techonology,Coimbatore, India, July 2014, 10.1109/ISVDAT.2014.6881084       Inproceedings

S. Pyne and A. Pal,"Energy efficient array initialization using loop unrolling with partial gray code sequence", in 17th International Symposium on VLSI Design and Test (VDAT 2013), vol.382, pp.83-93, Springer, Jaipur, India, July 2013, 10.1007/978-3/642-42024-5       Inproceedings

S. Pyne and A. Pal,"Branch target buffer energy reduction through efficient multiway branch translation techniques", Journal of Low Power Electronics, vol.8, no.5, pp.604 - 623, American Scientific Publishers, December 2012, doi:10.1166/jolpe.2012.1219       Article

S. Mitra and S. Pyne,"Fuzzy logic based route optimization in multihomed mobile networks", Wireless Networks, vol.17, no.1, pp.213-229, Springer, January 2011, 10.1007/s11276-010-0274-y       Article