U. Nanda, D. P. Acharya, P. K. Rout, and D. Nayak,"Modelling and Optimization of Phase Locked Loop under Constrained Channel Length and Width of MOSFETs", Silicon, vol.14, pp.1471–1477, Springer Netherlands, February 2022, https://doi.org/10.1007/s12633-021-00967-y       Article

J. K. Panigrahi and D. P. Acharya,"An Intelligent Sensing Framework for Post-Manufacturing Performance Measurement and Healing of CSVCO", IEEE Transactions on Instrumentation and Measurement, vol.72, pp.1-10, IEEE, November 2022, 10.1109/TIM.2022.3225039       Article

S. Roy, D. P. Acharya, and A. K. Sahoo,"Fast OMP algorithm and its FPGA implementation for compressed sensing-based sparse signal acquisition systems", IET Circuits, Devices & Systems, pp.1-11, IET 2021, 10.1049/cds2.12047       Article

U. Nanda, D. P. Acharya, D. Nayak, and P. K. Rout,"Modelling and Optimization of Phase Locked Loop under Constrained Channel Length and Width of MOSFETs", Silicon, Springer, January 2021, 10.1007/s12633-021-00967-y       Article

S. Roy, D. P. Acharya, and A. K. Sahoo,"Incremental Gaussian Elimination Approach to Implement OMP for Sparse Signal Measurement", IEEE Transactions on Instrumentation and Measurement, vol.69, no.7, pp.4067-4075, IEEE 2020, 10.1109/TIM.2019.2947118       Article

U. Nanda, D. P. Acharya, and D. Nayak,"Process Variation Tolerant Wide-band Fast PLL with Reduced Phase Noise using Adaptive Duty Cycle Control Strategy", International Journal of Electronics, vol.108, no.5, pp.705-717, Taylor & Francis, July 2020, https://doi.org/10.1080/00207217.2020.1793414       Article

S. Roy, D. P. Acharya, and A. K. Sahoo,"Low complexity architecture of orthogonal matching pursuit based on QR decomposition", IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol.27, no.7, pp.1623-1632, IEEE, April 2019, 10.1109/TVLSI.2019.2909754       Article

D. Nayak, D. P. Acharya, P. K. Rout, and U. Nanda,"A high stable 8T-SRAM with bit interleaving capability for minimization of soft error rate", Microelectronics Journal, vol.73, pp.43-51, Elsevier, March 2018, 10.1016/j.mejo.2018.01.008       Article

D. Nayak, D. P. Acharya, and K. Mahapatra,"A read disturbance free differential read SRAM cell for low power and reliable cache in embedded processor", AEU-International Journal of Electronics and Communications, vol.74, pp.192-197, Elsevier 2017, 10.1016/j.aeue.2017.02.012       Article

U. Nanda and D. P. Acharya,"Adaptive PFD selection technique for low noise and fast PLL in multi-standard radios", Microelectronics Journal, vol.64, pp.92-98, Elsevier, June 2017, 10.1016/j.mejo.2017.04.011       Article